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rev. 1.2 1/13 copyright ? 2013 by silicon laboratories SI5356A SI5356A i 2 c p rogrammable , a ny -f requency 1?200 mh z , q uad f requency 8-o utput c lock g enerator features applications description the si5356 is a highly flexible, i 2 c programmable clock generator capable of synthesizing four completely non-integer related frequencies up to 200 mhz. the device has four banks of outputs with each bank supporting two cmos outputs at the same frequency. using silicon laboratories' patented multisynth fractional divider technology, all outputs are guaranteed to have 0 ppm frequency synthesis error regardless of configuration, enablin g the replacement of multiple clock ics and crystal oscillators with a single device. each output bank is independently configurable to support 1.8, 2.5, or 3.3 v. the device is programmable via an i 2 c/ smbus-compatible serial interface and su pports operation fr om a 1.8, 2.5, or 3.3 v core supply. functional block diagram ? generates any frequency from 1 to 200 mhz on each of the 4 output banks ? programmable frequency configuration ? guaranteed 0 ppm frequency synthesis error for any combination of frequencies ? 25 or 27 mhz xtal or 5?200 mhz input clk ? eight cmos clock outputs ? easy to use programming software ? configurable ?triple a? spread spectrum: any clock, any frequency, and with any spread amount ? programmable output phase adjustment with <20 ps error ? interrupt pin indicates los or lol ? oeb pin disables all outputs or per bank oeb control via i 2 c ? low jitter: 50 ps pk-pk (typ), 75 ps pk-pk period jitter (max) ? excellent psrr performance eliminates need for external power supply filtering ? low power: 45 ma (core) ? core vdd: 1.8, 2.5, or 3.3 v ? separate vddo for each bank of outputs: 1.8, 2.5, or 3.3 v ? small size: 4x4 mm 24-qfn ? industrial temperature range: ?40 to +85 c ? printers ? audio/video ? dslam ? storage area networks ? switches/routers ? servers ordering information: see page 23. pin assignments xa clk5 clk4 vddoc vddob clk3 clk2 vdd vdd p2 clk6 clk7 los p3 vddoa clk1 clk0 gnd vddod gnd gnd xb p1 clkin p4 p5 top view 1 6 5 4 3 2 712 11 10 9 8 18 13 14 15 16 17 24 19 20 21 22 23 xa clk5 clk4 vddoc vddob clk3 clk2 vdd vdd scl clk6 clk7 intr sda vddoa clk1 clk0 gnd vddod gnd gnd xb i2c_lsb clkin ssc_dis oeb top view 1 6 5 4 3 2 712 11 10 9 8 18 13 14 15 16 17 24 19 20 21 22 23 free datasheet http://www.datasheet-pdf.com/
SI5356A 2 rev. 1.2 free datasheet http://www.datasheet-pdf.com/
SI5356A rev. 1.2 3 t able of c ontents section page 1. electrical specificat ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. typical application ci rcuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 3. functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 3.1. overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 3.2. input configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.3. breakthrough multisynth technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.4. frequency configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.5. configuring the si5356 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.6. output phase adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.7. cmos output drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.8. jitter performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.9. status indicators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 3.10. i2c interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 3.11. spread spectrum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.12. power supply considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4. si5356 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5. pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6. ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.1. evaluation board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7. package outline: 24-lead qfn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8. recommended pcb land pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 9. top marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 9.1. SI5356A top marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 9.2. top marking explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 document change list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 contact information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 free datasheet http://www.datasheet-pdf.com/
SI5356A 4 rev. 1.2 1. electrical specifications table 1. recommended operating conditions (v dd = 1.8 v ?5% to +10%, 2.5 or 3.3 v 10%, t a = ?40 to 85 c) parameter symbol test condition min typ max unit ambient temperature t a ?40 ? 85 o c core supply voltage v dd 2.97 3.3 3.63 v 2.25 2.5 2.75 1.71 1.8 1.98 output buffer supply voltage v ddo 1.71 ? 3.63 v note: all minimum and maximum specifications are guar anteed and apply across the recommended operating conditions. typical values apply at nominal supply vo ltages and an operating temperature of 25 c unless otherwise noted. table 2. dc characteristics (v dd = 1.8 v ?5% to +10%, 2.5 or 3.3 v 10%, t a = ?40 to 85 c) parameter symbol test condition min typ max unit core supply current i dd 100 mhz on all outputs, 25 mhz refclk ?4560ma output buffer supply current i ddox cmos, 50 mhz 15 pf load ?69ma cmos, 200 mhz 3.3 v vdd0 ?1318ma cmos, 200 mhz 2.5 v ?1014ma cmos, 200 mhz 1.8 v ?710ma high level input voltage v ih clkin, i2c_lsb 0.8 x v dd ?3.63 v ssc_dis, oeb 0.85 ? 1.3 v low level input voltage v il clkin, i2c_lsb ?0.2 ? 0.2 x v dd v ssc_dis, oeb ? ? 0.3 v clock output high level output voltage v oh pins: clk0?7 i oh =?4 ma v ddo ? 0.3 ? ? v clock output low level out- put voltage v ol pins: clk0?7 i ol =+4ma ??0.3v intr low level output voltage v olintr pin: intr i ol =+3ma 0?0.4v ssc_dis, oeb input resistance r in ?20?k ? free datasheet http://www.datasheet-pdf.com/
SI5356A rev. 1.2 5 table 3. ac characteristics (v dd = 1.8 v ?5% to +10%, 2.5 or 3.3 v 10%, t a = ?40 to 85 c) parameter symbol test condition min typ max unit input clock clock input frequency f in 5?200mhz clock input rise/fall time t r /t f 20?80% v dd ??2.3 ns 10?90% v dd ?? 4 ns clock input duty cycle dc input tr/tf within specified limits shown above 40 ? 60 % clock input capacitance c in ?2? pf output clocks clock output frequency f o 1?200mhz clock output frequency synthesis resolution f res see "3.4. frequency con- figuration" on page 11 001ppb output load capacitance c l ? ? 15 pf clock output rise/fall time t r /t f 20 to 80% v dd , c l = 15 pf ??2.0 ns clock output rise/fall time t r /t f 20 to 80% v dd , c l = 2 pf ? 0.45 0.85 ns clock output duty cycle dc measured at v dd /2 45 50 55 % powerup time t pu por to output clock valid ? ? 2 ms output enable time t oe ??10 s output-output skew t skew outputs at same frequency, f out > 5 mhz ?150 ? +150 ps period jitter j ppkpk 10000 cycles* ? 50 75 ps pk-pk cycle-cycle jitter j ccpk 10000 cycles* ? 40 70 ps pk phase jitter j ph 12 khz to 20 mhz ? 2 ? ps rms pll loop bandwidth f bw ?1.6? mhz interrupt status timing clkin loss of signal assert time t los ?2.6 5 s clkin loss of signal deassert time t los_b 0.01 0.2 1 s *note: measured in accordance to jedec standard 65. free datasheet http://www.datasheet-pdf.com/
SI5356A 6 rev. 1.2 table 4. crystal specifications parameter symbol test condition min typ max unit crystal frequency f xtal option 1 ? 25 ? mhz option 2 ? 27 ? mhz load capacitance (on-chip differential) c l (supported)* 11 12 13 pf c l (recommended) 17 18 19 pf crystal output capacitance c o ?? 5 pf equivalent series resistance esr 25 mhz ? ? 100 ? 27 mhz ? ? 75 ? crystal drive level rating d l 100 ? ? w *note: see "an360: crystal selection guide for si533x and si535 5/56 devices" for how to adjust the registers to accommodate a 12 pf crystal c l table 5. i 2 c specifications (scl,sda) 1 parameter symbol test condition standard mode fast mode unit min max min max low level input voltage v ili2c ?0.5 0.3 x v ddi2c ?0.5 0.3 x v ddi2c 2 v high level input voltage v ihi2c 0.7 x v ddi2c 3.63 0.7 x v ddi2c 2 3.63 v hysteresis of schmitt trigger inputs v hys n/a n/a 0.1 ? v low level output voltage (open drain or open collector) at 3 ma sink current v oli2c 2 v ddi2c 2 = 2.5/3.3 v 0 0.4 0 0.4 v v ddi2c 2 = 1.8 v n/a n/a 0 0.2 x v ddi2c v input current i ii2c ?10 10 ?10 10 a capacitance for each i/o pin c ii2c v in = ?0.1 to v ddi2c ?4 ? 4pf i 2 c bus timeout ?25352535ms notes: 1. refer to nxp?s um10204 i 2 c-bus specification and user manual, revision 03, for further details. 2. only i 2 c pull up voltages (vddi2c) of 1.71 to 3.63 v are supported. must write r egister 27[7] = 1 if the i 2 c bus voltage is less than 2.25 v. free datasheet http://www.datasheet-pdf.com/
SI5356A rev. 1.2 7 table 6. thermal conditions parameter symbol test condition value unit thermal resistance junction to ambient ? ja still air 37 c/w thermal resistance junction to case ? jc still air 25 c/w table 7. absolute maximum ratings 1,2,3,4 parameter symbol rating unit supply voltage range v dd ?0.5 to +3.8 v input voltage range (all pins except pins 1,2,5,6) v i ?0.5 to 3.8 v input voltage range (pins 1,2,5,6) v i2 ?0.5 to 1.3 v output voltage range v o ?0.5 to v dd + 0.3 v junction temperature t j ?55 to +150 o c esd tolerance hbm 2.5 kv cdm 550 v mm 175 v latch-up tolerance lu jesd78 compliant soldering temperature (pb-free profile) 5 t peak 260 o c soldering temperature time at t peak (pb-free profile) 5 t p 20?40 sec notes: 1. permanent device damage may occur if the absolute maximum ratings are exceeded. functional operation should be restricted to the conditions as specifie d in the operational sections of this data sheet. exposure to maximum rating conditions for extended periods may affect device reliability. 2. 24-qfn package is rohs compliant. 3. for more packaging information, go to www.silabs.com/support/qualit y/pages/rohsinformation.aspx . 4. moisture sensitivity level is msl3. 5. the device is compliant with jedec j-std-020. free datasheet http://www.datasheet-pdf.com/
SI5356A 8 rev. 1.2 2. typical application circuits i 2 c bus i 2 c address = 111 0000 (0x70) or 111 0001 (0x71) +3.3v 1k 1k 1k ethernet phy si5356 4-port ethernet switch/router 33/66 mhz 125 mhz x x ethernet phy ethernet phy ethernet phy 22 18 14 10 9 25 mhz clk0 clk2 clk4 clk6 clk7 21 clk1 17 clk3 13 clk5 ethernet switch mcu/ processor 16 15 11 20 24 7 vddoa vddob vddoc vddod vdd vdd 1 2 4 25 mhz xtal xa xb clkin 25 mhz 25 mhz 25 mhz 23 gnd gnd pad 23 pad 5 6 ssc_dis oeb 8 intr 19 12 3 sda scl i2c_lsb +3.3 v 0.1 uf power supply decoupling capacitors (1 per vdd or vddox pin) rse rsh rsh rse note: see section 3.2 for information on selecting rse and rsh. i 2 c bus i 2 c address = 111 0000 (0x70) or 111 0001 (0x71) +3.3 v 1k 1k 1k si5356 laser printer x x 22 18 14 10 9 clk0 clk2 clk4 clk6 clk7 21 clk1 17 clk3 13 clk5 16 15 11 20 24 7 vddoa vddob vddoc vddod vdd vdd 1 2 4 25 mhz xtal xa xb clkin 23 gnd gnd pad 23 pad 5 6 ssc_dis oeb 8 intr 19 12 3 sda scl i2c_lsb processor 125 mhz ddr memory touchscreen controller usb controller print head paper tray lcd screen key pad 48 mhz 66/100 mhz ethernet phy 35.788 mhz x x +3.3 v 0.1 uf power supply decoupling capacitors (1 per vdd or vddox pin) rse rsh rsh rse note: see section 3.2 for information on selecting rse and rsh. free datasheet http://www.datasheet-pdf.com/
SI5356A rev. 1.2 9 3. functional description 3.1. overview the si5356 is a highly flexible, i 2 c programmable clock generator capable of synthesizing four independent frequencies up to 200 mhz. the device has four banks of outputs with each bank supporting two cmos outputs at the same frequency. the si5356 supports free-running mode of operation using an external crystal, or it can lock to an external clock for generating synchronous clocks. the output drivers support 1.8, 2.5, and 3.3 v cmos formats, and each output bank is independently configurable. adjustable output-to-output phase offsets are also available to compensate for pcb trace delays or for fine tuning of setup and hold margins. configuration and control of the si5356 is handled through the i 2 c/smbus interface. the device also provides the option of storing a user-definable clock configuration in its non-vol atile memory (nvm), which becomes the default clock configuration power-up. see section "3.5.1. ordering a custom nvm configuration" on page 12 for details. 3.1.1. clockbuilder? desktop software to simplify device configur ation, silicon labs has released the clockbuilder desktop. the software serves two purposes: to configure the si5356 with optimal configuration based on the desired frequencies, and to control the evb, when connected to a host pc. the optimal configuration can be saved from the software in text files that can be used in any system, which configures the device over i 2 c. clockbuilder desktop can be downloaded from www.silabs.com/ clockbuilder and runs on windows xp, windows vista, and windows 7. additionally, an nvm file can be generated using the nvm ? save for factory programming... menu option. an nvm file can be used by factory to prepare custom pre-programmed devices. free datasheet http://www.datasheet-pdf.com/
SI5356A 10 rev. 1.2 3.2. input configuration the si5356 input can be driven from either an external crystal or a reference clock. if the crystal input option is used, the si5356 operates as a free-running clock generator. in this mode of operation the device requires a low cost 25 or 27 mhz fundamental mode crystal connected across xa and xb as shown in figure 1. given the si5356?s frequency flexibility, the same crystal can be reused to generate any combination of output frequencies. custom frequency crystals are not required. the si5356 integrates the crystal load capacitors on-chip to reduce external component count. the crystal should be placed very close to the device to minimize stray capacitance. to ensure a stable and accurate output frequency, the recommended crystal specifications provided in table 4 on page 6 must be followed. see an360 for additional details regarding crystal recommendations. figure 1. connecting an xtal to the si5356 for synchronous timing applications, the si5356 can lock to a 5 to 200 mhz cmos reference clock. a typical interface circuit is shown in figure 2. a series termination resistor matching the driver?s output impedance to the impedance of the transmission line is recommended to reduce reflections. figure 2. interfacing cmos reference clocks to the si5356 control input signals to ssc_dis and oeb cannot exceed 1.3 v yet also need to meet the voh and vol specifications outlined in table 2 on page 4. when these inputs are driven from cmos sources, a resistive attenuator as shown in the typical application circuits must be used. suggested standard 1% resistor values for rse and rsh, when using a cmos source, are given below. 3.3. breakthrough multisynth technology modern timing architectures require a wide range of frequencies which are often non-integer related. traditional clock architectures address this by using a combination of single pll ics, 4-pll ics and discrete xos, often at the expense of bom complexity and power. the si5356 use patented multisynth technology to dramatically simplify timing architectures by integrating the frequency synthesis capability of 4 phase-locked loops (plls) in a single device, greatly minimizing size and power requirements versus traditional solutions. based on a fractional-n pll, the heart of the architecture is a low phase noise, high- frequency vco. the vco supplies a high frequency output clock to the multisynth block on each of the four independent output paths. each multisynth operates as a high-speed fractional divide r with silicon laboratories' proprietary phase error correction to divide down the vco clock to the required output frequency with very low jitter. the first stage of the multisynth architecture is a fractional-n divider which switches seamlessly between the two closest integer divider values to produce the exact output clock frequency with 0 ppm error. to eliminate phase error generated by this process, multisynth calculates the relative phase difference between the clock produced by the fractional-n divider and the desired output clock and dynamically adjusts the phase to match the ideal clock waveform. this novel approach makes it possible to generate any output clock frequency without sacrificing jitter performance. based on this architecture, each clock output can produce any frequency from 1 to 200 mhz. xb xa xtal si5356 clkin 50 rs si5356 cmos level rse ohms rsh ohms 1.8 v 1000 1580 2.5 v 1960 1580 3.3 v 3090 1580 free datasheet http://www.datasheet-pdf.com/
SI5356A rev. 1.2 11 figure 3. silicon labs' multisynth technology 3.4. frequency configuration the si5356 utilizes a single pll-ba sed architecture, four independent multisynth fractional output dividers, and a multisynth fractional feedback divider such that a single device provides the clock generation capability of four independent plls. unlike competitive multi-pll solutions, the si5356 can generate four unique non- integer related output frequencies with 0 ppm frequency error, with respect to the re ference, for any combination of output frequencies. in addition, any combination of output frequencies can be generated from a single reference frequency without having to change the crystal or reference clock frequency between configurations. frequency configurations are fully programmable by writing to device registers using the i 2 c interface. any combination of output frequencies ranging from 1 to 200 mhz can be configured on each of the device outputs. 3.5. configuring the si5356 the si5356 is a highly-flexible clock generator that is entirely configurable through its i 2 c interface. the device?s default configuration is stored in non-volatile memory (nvm) as shown in figure 4. the nvm is a one-time programmable memory (otp), which can store a custom user configuration at power-up. this is a useful feature for applications that need a clock present at power-up (e.g., for providing a clock to a processor). figure 4. si5356 memory configuration during a power cycle or a power-on reset (por), the contents of the nvm are copied into random access memory (ram), which sets the device configuration that will be used during operati on. any changes to the device configuration after power-up are made by reading and writing to registers in the ram space through the i 2 c interface. clockbuilder desktop (see "3.1.1. clockbuilder? desktop software" on page 9) can be used to easily configure register map files that can be written into ram (s ee ?3.5.2. creating a new configuration for ram? for de tails). alternatively, the register map file can be created manually with the help of the equations in an565. two versions of the si5356 are available. first, non- customized si5356 devices are available in which the ram can be configured in-circuit via i 2 c. these blank si5356 devices can also be field programmed using the si5338/56-prog-evb (see ?3 .5.4. writing a custom configuration to nvm?). second, custom factory- programmed si5356 devices are available that include a user-specified startup frequency configuration (example part number SI5356A-axxxxx-gm). fractional-n divider phase adjust phase error calculator divider select (div1, div2) f vco f out multisynth power-up/por i 2 c ram nvm (otp) default config free datasheet http://www.datasheet-pdf.com/
SI5356A 12 rev. 1.2 3.5.1. ordering a custom nvm configuration the si5356 is orderable with a factory-programmed custom nvm configuration. th is is the simplest way of using the si5356 since it generates the desired output frequencies at power-up or after a power-on reset (por). this default configur ation can be reconfigured in ram through the i 2 c interface after power-up (see ?3.5.2. creating a new configuration for ram?). the first step in ordering a custom device is generating an nvm file which defines the input and output clock frequencies and signal formats. this is easily done using the nvm ? save for factory programming... menu option in clockbuilder desktop. (see "3.1.1. clockbuilder? deskt op software" on page 9.) this windows based software allows the user to generate an nvm file, which is used by the factory to manufacture custom parts. each custom part is marked with a unique part number identifying the specific configuration (e.g., SI5356A-a0 0100-gm). consult your local sales re presentative for more details on ordering a custom si5356. 3.5.2. creating a new configuration for ram any si5356 device can be configured by writing to registers in ram through the i 2 c interface. a non- factory programmed device must be configured in this manner. when creating a custom ram configuration, use the following procedure: 1. create a device configuration (register map) using clockbuilder desktop (v3.0 or later; see "3.1.1. clockbuilder? desktop soft ware" on page 9) or manually using the equations in ?an565: configuring the SI5356A?. a. configure the frequency plan. b. configure the output driver format and supply voltage. c. configure initial phase offset (if desired). d. configure spread spectrum (if desired). 2. save the configuration using the options > save register map file or options > save c code header file, or create the regi ster contents by the conversions listed in an565. at this point, the new config uration can be written to the device ram according to th e instructions in ?3.5.3. writing a custom configuration to ram?. 3.5.3. writing a custom configuration to ram writing a new configuration (register map) to the ram consists of pausing the lol state-machine, writing new values to the ic accounting for the write-allowed mask given in an565, validating the input clock or crystal, locking the pll to the input with the new configuration, restarting the lol state-machine, and calibrating the vco for robust operation across temperature. the flow chart in figure 5 on page 13 enumerates the details: note: the write-allowed mask spec ifies which bits must be read and modified before writing the entire register byte (a.k.a. read-modify-write ). ?an428: jump start: in- system, flash-based programming for silicon labs? timing products? illustrates the procedure defined in section 3.5.2 with ansi c code. free datasheet http://www.datasheet-pdf.com/
SI5356A rev. 1.2 13 figure 5. i 2 c programming procedure 3.5.4. writing a custom configuration to nvm an alternative to ordering an si5356 with a custom nvm configuration is to use the field programming kit (si5338/56-prog-evb) to writ e directly to the nvm of a "blank" si5356. since nvm is an otp memory, it can only be written once. the default configuration can be reconfigured by writing to ram through the i 2 c interface (see ?3.5.2. creating a new configuration for ram?). 3.6. output phase adjustment the si5356 has a digitally-controlled phase adjustment feature that allows the user to adjust the phase of each output clock in relation to the other output clocks. the phase of each output clock can be adjusted with an error of <20 ps over a range of 45 ns. this feature is available on any clock output that does not have spread spectrum enabled. 3.7. cmos output drivers the si5356 has 4 banks of outputs with each bank comprised of 2 clocks for a to tal of 8 cmos outputs per device. by default, each b ank of cmos output clocks are in-phase. alternatively, each output clock can be inverted. this feature enables each output pair to operate as a differential cmos clock. each of the output banks can operate from a different vddo supply (1.8 v, 2.5 v, 3.3 v), simplifying usage in mixed supply applications. the cmos output driver has a controlled impedance of close to 50 ??? which includes an internal 22 ? series resistor. an external series resistor is not needed when driving 50 ? traces. if higher impedance traces are used then a series resistor may be added. a typical configuration is shown in figure 6. 3.8. jitter performance the si5356 provides consistently low jitter for any combination of output frequencies. the device leverages a low phase noise single pll architecture and silicon laboratories? pate nted multisynth fractional output divider technology to deliver excellent jitter performance guaranteed across process, temperature and voltage. the si5356 provides superior performance to traditional multi-pll solu tions which may suffer from degraded jitter performance depending on frequency plan and the number of active plls. register map use clockbuilder desktop v3.0 or later set reg241 = 0x65 write new configuration to device accounting for the write-allowed mask (see an565: configuring the SI5356A) disable outputs set oeb_all = 1; reg230[4] if using down-spread: set ms_reset = 1; reg 226[2] = 1 wait 1 ms set ms_reset = 0; reg 226[2] = 0 apply soft reset set soft_reset = 1; reg246[1] enable outputs set oeb_all = 0; reg230[4] free datasheet http://www.datasheet-pdf.com/
SI5356A 14 rev. 1.2 3.9. status indicators an open-drain interrupt pin (intr) is available to indicate a loss of signal (los) conditi on, a pll loss of lock (lol) condition, or th at the pll is in the proc ess of acquirin g lock (sys_cal). as shown in figure 7, a status register at address 218 is available to help identify the exact even t that caused the interrupt pin to become active. a los condition occurs when there is no clock input to the si5356. the loss of lock algorithm works by continuously monitoring the frequency difference between the two inputs of the phase frequency detector. when this frequency difference is greater than about 1000 ppm, a loss of lo ck condition is declared. no te that the vco will track the input clock frequency for up to ap proximately 25000 ppm, which will ke ep the inputs to th e phase frequency detector at the same frequency until the pll comes out of lock. when a clock input is removed, the interrupt pin will assert, and the clock outputs may drift up to 5%. when the input clock is re applied with an appropriate frequency, the pll will again lock. figure 6. cmos output driver configuration multisynth bank a +1.8v, +2.5v, +3.3v vddoa clk0 clk1 multisynth bank c +1.8v, +2.5v, +3.3v vddoc clk4 clk5 multisynth bank d +1.8v, +2.5v, +3.3v vddod clk6 clk7 multisynth bank b +1.8v, +2.5v, +3.3v vddob clk2 clk3 pll 50 50 50 50 50 50 50 50 si5356 free datasheet http://www.datasheet-pdf.com/
SI5356A rev. 1.2 15 3.10. i 2 c interface the si5356 control interface is a 2-wire bus for bidirectio nal communication. the bus consists of a bidirectional serial data line (sda) and a serial clock input (scl). th e device operates as a slave device on the 2-wire bus and is compatible with i 2 c specifications. both lines must be connected to the positive supply via an external pull-up. standard-mode (100 kbps) and fast-mode (400 kbps) operation and 7-bit addressing are supported as specified in the i 2 c-bus specification standard. to accommodat e multiple si5356 devices on the same i 2 c bus, the si5356 has pin 3 as i2c_lsb. the complete 7-bit i2c bus address for the device is 70h or 71h depending upon the state of the i2c_lsb pin. in binary, this is written as 111 000[i2c_lsb]. see figure 8 for the command format for both read and write access. data is always sent msb first. table 5 includes the ac and dc electrical parameters for the scl and sda i/os, respectively. the timing specificat ions and timing diagram for the i 2 c bus can be found in the i 2 c-bus specification standard. sda timeout support is supported for compatib ility with smbus interfaces. the i 2 c interface is 3.3 v tolerant. the i 2 c bus can be operated at a bus voltage of 1.71 to 3. 63 v and should have a pullup resistor as recommended by the i 2 c-bus specification. if the i 2 c bus voltage is less than 2.25 v, register 27[7] must be set to 1. figure 7. status register 218 0 1 2 3 4 5 6 7 los xtal los clk sys cal lol system calibration (lock acquisition) loss of signal xtal input loss of signal clock input loss of lock free datasheet http://www.datasheet-pdf.com/
SI5356A 16 rev. 1.2 figure 8. i 2 c/smbus-compatible command format 3.11. spread spectrum to help reduce electromagnetic interf erence (emi), the SI5356A supports sp read spectrum modulation. the output clock frequencies can be modulated to spread energy across a broader range of fr equencies, lowering system emi. the SI5356A implements spread spectrum using its pa tented multisynth technology to achieve previously unattainable precision in both modulation rate and spreading magnitude as shown in figure 9. through i 2 c control, the spread spectrum can be applied to any output clock, any clock frequency, and any spread amount from 0.1% to 2.5% center spread and ?0.1% to ?5% down spread . the spreading rate is limited to 30 to 63 khz. the spread spectrum is generated digitally in the ou tput multisynths which means that the spread spectrum parameters are virtually independent of process, volt age, and temperature variations. since the spread spectrum is created in the output multisynths, through i 2 c each output channel can hav e independent spread spectrum parameters. without the use of i 2 c (nvm download only) the only supported spread spectrum parameters are for pci express compliance composing 10 0 mhz clock, 31.5 khz spreading fr equency with the choice of the spreading. rev a devices provide native support for both down and center spread. center spread is supported in rev b devices by up-shifting the nominal frequency and usin g down-spread register para meters. consult an565 for details. note: if you currently use center spread on a revision a and would like to migrate to a revision b device, you must generate a new register map using either clockbuilder desktop or th e equations in an565. center spread configurations for revisions a and b are not compatible. from master to slave from slave to master 1 ? read 0 ? write a ? acknowledge (sda low) n ? not acknowledge (sda high). required after the last data byte to signal the end of the read comand to the slave. s ? start condition p ? stop condition repeated start read write a reg addr [7:0] a s slv addr [6:0] 0 s slv addr [6:0] 1 a a data [7:0] n p data [7:0] a a reg addr [7:0] a s slv addr [6:0] 0 a data [7:0] data [7:0] p read data a data [7:0] a s slv addr [6:0] 1 n p data [7:0] write data a reg addr [7:0] a s slv addr [6:0] 0 p two command read optional optional optional free datasheet http://www.datasheet-pdf.com/
SI5356A rev. 1.2 17 figure 9. configurable spread spectrum -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -10% -8% -6% -4% -2% 0% 2% 4% 6% 8% 10% relative f requency relative power (db ) 1.0% 2.5% 5.0% no spread free datasheet http://www.datasheet-pdf.com/
SI5356A 18 rev. 1.2 3.12. power supply considerations the si5356 has two core supply voltage pins (v dd ) and four clock output bank supply voltage pins (v ddoa ? v ddod ), enabling the device to be used in mixed supply app lications. the si5356 does not require ferrite beads for power supply filtering. the device has extensive on-chip power supply regulation to minimize the impact of power supply noise on output jitter. figure 10 is a curve of additive phase jitter with power supply noise. note that even when a significant amount of noise is applied to the device power supply, ad ditive phase jitter is still very small. figure 10. peak-to-peak additive phase jitter from 100 mv sine wave on supply free datasheet http://www.datasheet-pdf.com/
SI5356A rev. 1.2 19 4. si5356 registers for many applications, the si5356's register values are easily configured using clockbuilder desktop (see "3.1.1. clockbuilder? desktop software" on page 9). however, for customers interested in using the si5356 in operating modes beyond the capab ilities available with clockbuilder, refer to ?a n565: configuring the si 5356a? for a detailed description of the si5356 registers and their usage. also refer to ?an428: jump start: in-system, flash-based programming for silicon labs? timing products? for a working application example of register prog ramming using the silicon labs' c8051f301 mcu. free datasheet http://www.datasheet-pdf.com/
SI5356A 20 rev. 1.2 5. pin descriptions note: center pad must be tied to gnd for normal operation. table 8. si5356 pin descriptions pin # pin name i/o description 1xa i external crystal. if a 25 or 27 mhz crystal is used as the dev ice frequency reference, connect it across xa and xb. if no input clock is used, this pin should be tied to gnd. 2xb i external crystal. if a 25 or 27 mhz crystal is used as the dev ice frequency reference, connect it across xa and xb. if no input clock is used, this pin should be tied to gnd. 3 i2c_lsb i i 2 c lsb address bit (3.3 v tolerant). this pin is the least significant bit of the si5356 i 2 c address allowing up to two si5356 devices to occupy the same i 2 c bus. 4clkin i single-ended input clock. if a single-ended clock is used as the device frequency reference, connect it to this pin. this pin functions as a high-impedance inpu t for cmos clock signals. the input should be dc coupled. if a crystal is used as the device frequency reference, this pin should be tied to gnd. xa clk5 clk4 vddoc vddob clk3 clk2 vdd vdd scl clk6 clk7 intr sda vddoa clk1 clk0 gnd vddod gnd gnd xb i2c_lsb clkin ssc_dis oeb top view 1 6 5 4 3 2 712 11 10 9 8 18 13 14 15 16 17 24 19 20 21 22 23 free datasheet http://www.datasheet-pdf.com/
SI5356A rev. 1.2 21 5 ssc_dis i spread spectrum disable. this pin allows disabling of the spread spectr um feature on the output clocks. note that the maximum voltage level on this pin must not exceed 1.3 v. to disable spread spec- trum connect this pin to a voltage of 0.85 to 1.3 v. connect to gnd to enable spread spectrum. a resistor voltage divider is recommended when controlled by a signal greater than 1.3 v. see the typical application circuit for details. 6oeb i output enable (active low). this pin allows disabling the output clocks. note that the maximum voltage level on this pin must not exceed 1.3 v. to disable all output s connect this pin to a voltage of 0.85 to 1.3 v. connect to gnd to enable all outputs. a resistor voltage divider is recommended when controlled by a signal greater than 1. 3 v. see the typical application circuit for details. 7vddvdd core supply voltage. the device operates from a 1.8, 2.5, or 3.3 v supply. a 0.1 f bypass capacitor should be located very close to this pin. 8intro interrupt. a typical pullup resistor of 1?4 k ? should be used on this pin. this pin functions as an maskable interrupt output. 0 = no interrupt 1 = interrupt present this pin is open drain and requires an external > 1k ? pullup resistor. 9clk7o output clock 7. cmos output clock. if unused, this pin must be left floating. 10 clk6 o output clock 6. cmos output clock. if unused, this pin must be left floating. 11 vddod vdd clock output bank d supply voltage. power supply for clock outputs 6 and 7. may be operated from a 1.8, 2.5, or 3.3 v sup- ply. a 0.1 f bypass capacitor should be located very close to this pin. if clk6/7 are not used, this pin must be tied to pin 7 and/or pin 24 or a voltage rail > 1.5 v. 12 scl i i 2 c serial clock input (3.3 v tolerant). 13 clk5 o output clock 5. cmos output clock. if unused, this pin must be left floating. 14 clk4 o output clock 4. cmos output clock. if unused, this pin must be left floating. 15 vddoc vdd clock output bank c supply voltage. power supply for clock outputs 4 and 5. may be operated from a 1.8, 2.5 or 3.3 v sup- ply. a 0.1 f bypass capacitor should be located very close to this pin. if clk4/5 are not used, this pin must be tied to pin 7 and/or pin 24 or a voltage rail > 1.5 v. 16 vddob vdd clock output bank b supply voltage. power supply for clock outputs 2 and 3. may be operated from a 1.8, 2.5, or 3.3 v sup- ply. a 0.1 f bypass capacitor should be located very close to this pin. if clk2/3 are not used, this pin must be tied to pin 7 and/or pin 24 or a voltage rail > 1.5 v. 17 clk3 o output clock 3. cmos output clock. if unused, this pin must be left floating. table 8. si5356 pin descriptions (continued) free datasheet http://www.datasheet-pdf.com/
SI5356A 22 rev. 1.2 18 clk2 o output clock 2. cmos output clock. if unused, this pin must be left floating. 19 sda i/o i 2 c serial data (3.3 v tolerant). 20 vddoa vdd clock output bank a supply voltage. power supply for clock outputs 0 and 1. may be operated from a 1.8, 2.5, or 3.3 v sup- ply. a 0.1 f bypass capacitor should be located very close to this pin. if clk0/1 are not used, this pin must be tied to pin 7 and/or pin 24 or a voltage rail > 1.5 v. 21 clk1 o output clock 1. cmos output clock. if unused, this pin must be left floating. 22 clk0 o output clock 0. cmos output clock. if unused, this pin must be left floating. 23 gnd gnd ground. must be connected to system ground. minimize the ground path impedance for optimal performance of the device. 24 vdd vdd core supply voltage. the device operates from a 1.8, 2.5, or 3.3 v supply. a 0.1 f bypass capacitor should be located very close to this pin. gnd pad gnd gnd ground pad. this is the large pad in the center of the package. the dev ice will not func tion unless the ground pad is properly connected to a ground plane on the pcb. see "8. recom- mended pcb land pattern" on page 25 for the pcb pad sizes and ground via require- ments. table 8. si5356 pin descriptions (continued) free datasheet http://www.datasheet-pdf.com/
SI5356A rev. 1.2 23 6. ordering guide 6.1. evaluation board SI5356A bxxxxx gmr i 2 c programmable any-frequency 1?200 mhz quad frequency 8-output clock generator b = product revision b xxxxx = 5-digit custom code assigned to each unique device configuration. leave xxxxx blank for standard factory default configuration (SI5356A-b-gmr) gmr = tape & reel gm = trays contact your silicon labs sales representative for details regarding shipment media. si5356 evb si5356 evaluation board free datasheet http://www.datasheet-pdf.com/
SI5356A 24 rev. 1.2 7. package outline: 24-lead qfn figure 11. 24-lead quad flat no-lead (qfn) table 9. package dimensions dimension min nom max a 0.80 0.85 0.90 a1 0.00 0.02 0.05 b 0.18 0.25 0.30 d 4.00 bsc. d2 2.35 2.50 2.65 e 0.50 bsc. e 4.00 bsc. e2 2.35 2.50 2.65 l 0.30 0.40 0.50 aaa 0.10 bbb 0.10 ccc 0.08 ddd 0.10 eee 0.05 notes: 1. all dimensions shown are in milli meters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to the jede c outline mo-220, variation vggd-8. 4. recommended card reflow profile is per the jedec/ip c j-std-020 specification for small body components. 5. j-std-020 msl rating: msl3. 6. terminal base alloy: cu. 7. terminal plating/grid array material: au/nipd. 8. for more packaging information, go to www.silabs.com/support/quality/ pages/rohsinformation.aspx . free datasheet http://www.datasheet-pdf.com/
SI5356A rev. 1.2 25 8. recommended pcb land pattern table 10. pcb land pattern dimension min nom max p1 2.50 2.55 2.60 p2 2.50 2.55 2.60 x1 0.20 0.25 0.30 y1 0.75 0.80 0.85 c1 3.90 c2 3.90 e0.50 notes: general 1. all dimensions shown are in milli meters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994 specification. 3. this land pattern design is based on the ipc-7351 guidelines. 4. connect the center ground pad to a ground plane with no less than five vias. these 5 vias should have a length of no more than 20 mils to the ground plane. via drill size should be no smaller than 10 mils. a longer distance to the ground plane is allowed if more vias are used to keep the inductance from increasing. solder mask design 5. all metal pads are to be non-solder mask defined (nsmd). clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. stencil design 6. a stainless steel, laser-cut and electro-polished stencil wit h trapezoidal walls should be used to assure good solder paste release. 7. the stencil thickness should be 0.125 mm (5 mils). 8. the ratio of stencil aperture to land pad size should be 1:1 for all perimeter pins. 9. a 2x2 array of 1.0 mm square openings on 1.25 mm pitch should be used for the center ground pad. card assembly 10. a no-clean, type-3 solder paste is recommended. 11. the recommended card reflow profile is per the jedec/ ipc j-std-020 specification for small body components. free datasheet http://www.datasheet-pdf.com/
SI5356A 26 rev. 1.2 9. top marking 9.1. SI5356A top marking 9.2. top marking explanation mark method: laser line 1 marking: device part number si5356 line 2 marking: a = frequency and configuration code. i 2 c programmable, any-frequency 1?200 mhz, quad frequency, 8-output clock generator. xxxxx = nvm code for custom factory- programmed devices (characters are not included for blank devices). see ordering guide section in data sheet for more information. axxxxx line 3 marking: r = product revision. ttttt = manufacturing trace code. rttttt line 4 marking: pin 1 indicator. circle with 0.5 mm diameter; left-justified yy = year. ww = work week. characters correspond to the year and work week of package assembly. yyww yyww rttttt axxxxx si5356 free datasheet http://www.datasheet-pdf.com/
SI5356A rev. 1.2 27 d ocument c hange l ist revision 0.1 to revision 0.2 ? improved specification details on input signals. ? added phase and cycle-cycle jitter specifications. ? added thermal resistance junction to case. ? improved application circuits. ? added gnd via requirement details. ? added differential cmos capability. revision 0.2 to revision 0.3 ? added section ?3.1. overview? ? updated section ?3.2. input configuration? ? updated section ?3.4. frequency configuration? ? added section ?3.5. configuring the si5356? ? added section ?4. si5356 registers? ? added section ?9. top marking? ? updated ?figure 10. peak-to-peak additive phase jitter from 100 mv sine wave on supply? revision 0.3 to revision 1.0 ? renamed part number on page header from si5356 to SI5356A. ? updated table 2. dc characteristics. ?? added iddox specification. ?? corrected pn input resi stance specification. ? updated table 3, ?ac characteristics,? on page 5. ?? added 10?90% input clock rise/fall time. ?? added los assert/deassert time. ?? added note on jitter test. ?? updated 20?80% rise/fall time with c l = 15 pf for output clocks to the ma ximum value of 2.0 ns. ?? changed frequency synthesis resolution spec to the correct value of 1ppb max. ? updated recommended crysta l load parameters in table 4 on page 6. ? updated table 6 on page 7. ?? added soldering profile specification ?? corrected input voltage range (v i2 ) to 1.3 v (max). ?? added packaging/rohs information. ? removed section ?3.5.4. modifying a multisynth output divider ratio/frequency configuration.? ? removed output-to-output sk ew spec from text in section "3.7. cmos output drivers" to prevent duplicating spec in ?table 3. ac characteristics.? ? removed jitter spec from te xt in section "3.8. jitter performance" to prevent duplicating spec in ?table 3. ac characteristics.? ? added evaluation board information to the ordering guide. revision 1.0 to revision 1.1 ? updated figure 5 on page 13 to provide workaround for spread spectrum errata. ? added " document change list" on page 27. revision 1.1 to revision 1.2 ? removed down spread spectrum errata that has been corrected in revision b. ? updated ordering information to refer to revision b silicon. ? updated top marking explanation in table. ? added further explanation to describe revision- specific behavior of center spread spectrum in section 3.11 free datasheet http://www.datasheet-pdf.com/
SI5356A 28 rev. 1.2 c ontact i nformation silicon laboratories inc. 400 west cesar chavez austin, tx 78701 tel: 1+(512) 416-8500 fax: 1+(512) 416-9669 toll free: 1+(877) 444-3032 please visit the silicon labs technical support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. patent notice silicon labs invests in research and development to help our cust omers differentiate in the market with innovative low-power, s mall size, analog- intensive mixed-signal solutions . silicon labs' extensive patent portfolio is a testament to our unique approach and world-clas s engineering team silicon laboratories, silicon labs, and clockbuilder are trademar ks of silicon laboratories inc. other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. the information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. silicon laboratories assumes no responsibility for errors and omissions, and disclaims responsib ility for any consequences resu lting from the use of information included herein. a dditionally, silicon laboratorie s assumes no responsibility for the functioning of und escribed features or parameters. silicon laboratories reserves the right to make changes without further notice . silicon laboratories makes no wa rranty, rep- resentation or guarantee regarding the suitability of its products for any particular purpose, nor does silicon laboratories as sume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any an d all liability, including wi thout limitation conse- quential or incidental damages. silicon laborat ories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the silicon laboratories product could create a s ituation where per- sonal injury or death may occur. should buyer purchase or us e silicon laboratories products for any such unintended or unauthor ized ap- plication, buyer shall indemnify and hold silicon laboratories harmless against all claims and damages. free datasheet http://www.datasheet-pdf.com/

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